NCP1603D100R2G【PDF 21/30 页】IC CTLR PFC/PWM COMBO 16-SOIC

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Sheet目录45

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NCP1603

http://onsemi.com

Figure 54 illustrates the standby detection circuitry and

its timing diagram. When standby condition happens (i.e.,

FB2

< 0.75 V), the controller will wait for a typical 125 ms

to ensure that the output power remains low for a while.

Then, the V

aux

is disabled to shut down the PFC section for

power saving. The V

aux

(or the PFC) restores when V

FB2

goes above 1.25 V immediately because V

FB2

can be

possibly above the 0.75 V threshold during standby

operation (referring to Figure 55) and the PFC section is

needed after the circuit restores from standby condition.

Figure 55. Timing Diagram in Standby Condition

CC2

FB2

Out2 goes low (no drain current) when V

FB2

< 0.75 V

CC2

needs to be above 7.7 V to ensure

proper operation of the controller and

main output within regulation

1.25 V

0.75 V

7.7 V

time

Figure 56. Block Diagram in Standby Operation in

PWM Section

CS2

FB2

Vcc2

Out2

PWM

clock

0.75 V

Standby

FB2

Figure 55 and 56 show the timing diagram and block

diagram of the standby operation respectively. A skipping

cycle behavior of the drain current is made by reset the

latch whenever V

FB2

is smaller than 0.75 V. When V

FB2

greater than 0.75 V, the duty ratio is modulated by the

PWM block that is illustrated in Figure 50.

PFC in Discontinuous/Critical Mode

The PFC section of the NCP1603 is NCP1601 that is

designed for lowpower PFC boost circuit in DCM or CRM

and takes advantages on both operating modes. DCM limits

the maximum switching frequency. It simplifies the

frontended EMI filter design. CRM limits the maximum

currents of diode, MOSFET and inductor. It reduces the

costs and improves the reliability of the circuit. This device

substantially exhibits unity power factor while operating in

DCM and CRM. It minimizes the number of external

components.

The PFC section primarily designed to operate in

fixedfrequency DCM. In the most stressful conditions,

CRM can be an alternative option that is without power

factor degradation. On the other hand, the PFC section can

be viewed as a CRM controller with a frequency clamp

(maximum switching frequency limit) alternative option

that is also without power factor degradation. In summary,

the PFC section can cover both CRM and DCM without

power factor degradation. Based on the selections of the

boost inductor and the oscillator frequency, the circuit is

capable of the following three applications.

1. CRM only by setting the oscillator frequency

higher than the CRM frequency range.

2. CRM and DCM by setting the oscillator

frequency somewhere within the CRM frequency

range.

3. DCM only by setting the oscillator frequency

lower than the CRM frequency range.

Figure 57. Timing Diagram of the PFC Stage

critical mode

DCM

time

current

time

ton

control

Inductor current, I

Input current, I

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